Meeting date: 21 feb 2006
Members (asterisk for those attending):
*Arpad Murayni,
*Bob Ross,
Todd Westerhoff,
*Mike LaBonte,
Paul Fernando,
Barry Katz,
*Walter Katz,
Ken Willis,
Ian Dodd

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Review of ARs:

AR: Mike make the website more outsider-friendly
- TBD

AR: Todd contact Cadence about a new representative
- no report

AR: Mike finish documentation examples.
- in progress

AR: Todd contact Ian
- no report

AR: Bob contact Gary Pratt
- Done - Gary can't fill in for Ian
- Walter sent an email - Out of Office

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Mentor AMS models for RocketIO and PCI-X 
- DesignCon discussion with Walter and Gary Pratt
  - Walter asked for RocketIO and PCI-X VHDL models
  - One is released already, the other coming soon
  - Buffers are actually very simple, probably easy to convert
- Walter built a template in native ISPICE4
  - Invented I/V curves, etc. based on descriptions given
  - Sent to Arpad
  - Format is neutral, not any particular language
  - Includes macro for trigerrable PWL
    - used for pullup/pulldown switching
    - able to reverse if overclocked
- Pre-emphasis buffer not created cadence-style (main+inv. secondary)
  - Arpad hesitant to create special macro element for this

AR: Arpad look at Walter's model

Triggerable sources
- Kai from Synopsys says there is an obscure way to
  create triggered sources in HSPICE
- Not sure how to do it in Verilog-A, but Gary Pratt
  says it can be done
- Are IBIS waveforms needed for serdes buffers?
  - switching may be linear, but how to determine
    pullup/pulldown turnoff/turnon separation?
- HSPICE has trouble with rwf & fwf parameters

DesignCon VHDL simulation paper
- Micron memory testcase
- I/V described as polynomials
- Contains VHDL core code to send bit patterns
- DDR1 interface only, don't have VHDL for DDR2
- Looked pretty good

Mentor has released Intel Broadwater VHDL-AMS models
- pre-emphasis serdes buffer
- IBIS format
  - both [Driver Schedule] and [External Model]
- NDA required

DesignCon had interesting equalization papers
- Equalization is an important problem to solve
- It may be quite complicated
- Good opportunity for macro models
- May change the way simulations are scheduled, or
  the combination of things analyzed in one simulation
- Need to handle feedback designs, where the receiver
  reports quality data back to the transmitter

Should buffer macros be strength scalable?
- How to scale waveforms
  - probably less scaling there than I/V
- HSPICE does it, but issues
- dangerous

AR: Arpad make buffers scalable

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Next meeting: Tuesday 07 mar 2006 12:00pm PT